EDN

Synopsys announces SystemVerilog testbench

At the SNUG (Synopsys Users Group) East meeting this week in Boston, Synopsys will release Pioneer-NTB, its new automatic testbench-verification system supporting the SystemVerilog design and ...
EDN

Using advanced logging techniques to debug & test SystemVerilog HDL code

SystemVerilog provides an advantage in addressing the verification complexity challenge—not simply as a new language for describing complex structures, but as a platform for driving a more efficient, ...
Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

The SystemVerilog infrastructure is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of ...
Design-Reuse

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
Design-Reuse

Synopsys Advances VCS Solution by Adding Assertion IP Library and Native Testbench Support for SystemVerilog

Latest version of the VCS® solution speeds standards-based verification by unifying SystemVerilog and SystemCâ„¢ languages in a single tool MOUNTAIN VIEW, Calif., May 31, 2005-- Synopsys, Inc. (Nasdaq ...