No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital ...

Hierarchical test methodologies are being broadly adopted for large designs. They provide roughly an order of magnitude better ATPG (automatic test program generation) run time, reduce workstation ...

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging.

The Material Design team has an interesting blog post into what it calls the “24-hour Clock Design Challenge” that chronicles Google’s work creating a time picker for those that use a 24-hour format ...

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...

Yesterday’s SoCs are today’s blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this ...

ZURICH (Reuters) - Apple, sensitive about protecting its own designs, has struck a deal to use Swiss railway operator SBB's trademark station clock design on iPads and iPhones. SBB, which holds the ...

The Design School will display a collection of clocks on Wednesday, Nov. 1, from 9 a.m. to 5 p.m. Though the 12-inch clocks all have ticking hands, their primary functions are not to tell time, but to ...