Tech Xplore on MSN

New semiconductor etching process achieves five-fold speed improvement

After more than a decade of research and development, Tokyo Electron Miyagi Ltd. has introduced an innovative semiconductor ...
Semiconductor Engineering

Cryogenic Etch: A Key Enabler Of 3D NAND

Released every 12 to 18 months, 3D NAND scaling outpaces most other semiconductor devices in replacement rate and performance ...
Business Wire

Hitachi High-Technologies Develops Leading Edge High-k/Metal Gate Etch Processes for Flash and Logic Chips

DALLAS--(BUSINESS WIRE)--July 11, 2006--Hitachi High-Technologies America, Ltd. today announced that it is working with multiple leading integrated device manufacturers (IDMs) to develop new high-k ...
Semiconductor Engineering

Improving Gate All Around Transistor Performance Using Virtual Process Window Exploration

As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF [1]. One method to overcome this problem is to move away from planar ...
EDN

IMEC improves performance for 32-nm simplified high-k/metal gate process

At the VLSI Symposium being held this week in Honolulu, Hawaii, Leuven, Belgium-based nanotechnology research center IMEC reported that it has improved performance for its planar CMOS semiconductor ...
Yahoo Finance

ACM Research Enters Bevel Etch Market to Support Emerging Process Steps in 3D NAND, DRAM and Advanced Logic Manufacturing

FREMONT, Calif., Aug. 05, 2021 (GLOBE NEWSWIRE) -- ACM Research, Inc. (“ACM”) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging ...
EurekAlert!

Researchers create a new etching method to improve smartphone circuit performance

In circuitry, etching is used to remove the deformed layer created during the grinding and polishing of metal components by selective chemical attack. Now, a research group at Nagoya University in ...
EDN

Applied packs critical-dimension metrology in new etcher

SAN FRANCISCO — Applied Materials Inc. here at Semicon West announced a silicon-etch tool featuring integrated metrology for critical-dimension measurements in sub-100-nm process technologies. Applied ...
Electronic Design

Simplified High-k/Metal-Gate Process Increases Planar CMOS Speed

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...
Design-Reuse

Antenna Effect in 16nm Technology Node

This paper describes the antenna effect observed in the 16nm design and the way to identify antenna violations in design using different PV tool. We have described three different methods to fix the ...
AZOM

Atomic Layer Deposition and Atomic Layer Etching for GaN Power Electronics

New GaN power electronics are being developed for power conversion and delivery. In electric transportation such as Electric and Hybrid Electric Vehicles (EV and HEV), these devices are becoming ...