EDN

Network tester checks jitter for 10G XFP

Configured with the optional differential I/O feature and 2.5G/10G 1,310/1,550-nm optical interface, the MP1590B network performance tester can measure the pattern-dependent jitter characteristics of ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
EDN

ON Semiconductor Introduces Programmable Clock Multiplier with Best-in-Class Jitter Performance for Networking and Consumer Applications

The NB3N3020 can generate up to 26 different clock frequencies from single input source on its LVPECL/ LVCMOS output, providing design flexibility and system cost savings ON Semiconductor has ...
Tech Times

Gaming Network Upgrades: Proven Ways to Reduce Latency and Achieve Stable Internet Gaming

Discover essential gaming network upgrades that reduce latency and boost stable internet gaming, helping players enjoy ...
TechJuice

PTA Flags Several Broadband Operators for QoS Shortcomings, Orders Fixes

The survey revealed that network availability, latency, and jitter remain major challenges for certain operators. Core node ...